Semiconductor memory devices are generally organized in a bidimensional array memory matrix) wherein the single memory elements are located at the intersection or rows ("word lines") and columns ("bit lines") of the matrix. To access a given memory element, it is necessary to select the word line and the bit line at the intersection of which said memory element is located; to this purpose, the memory address bus is divided into row and column address signals, which are decoded independently.
It is known that in the manufacture of semiconductor memories defects are frequently encountered that afflict a limited number of memory elements in the memory matrix. The reason for the high probability or detects of this type is that, in a semiconductor memory device, the greatest part of the chip area is occupied by the memory matrix; moreover, it is in the memory matrix, and not in the peripheral circuitry, that the manufacturing process characteristics are usually pushed to limits.
In order to avoid that the presence of a limited number of defective memory elements, from many millions of memory elements, threes the rejection of the entire chip, and therefore to increase the manufacturing process yield, the technique is known of providing for the manufacture of a certain number or additional memory elements, commonly called "redundancy memory elements," to be used as a replacement of those elements that, during testing or the memory device, prove defective. The selection circuits, with which the integrated component must necessarily be provided, and which allow the above-mentioned functional replacement of a defective memory element with a redundancy memory element, are indicated as a whole with the name of "redundancy circuitry," while the set or redundancy memory elements and circuitry is defined in short as "redundancy."
The redundancy circuitry comprises programmable non-volatile memory registers (redundancy registers) suitable to store those address configurations corresponding to the defective memory elements. Such registers are programmed once and for all during the memory device testing, and must retain the information stored therein even in absence of the power supply.
In practical implementations of redundancy in memory devices, both word lines and bit lines of redundancy memory elements are generally provided in the memory matrix. Each redundancy word line or bit line is associated with a respective row or column redundancy register wherein the address of a defective word line or bit line is stored so that, whenever the defective word line or bit line is addressed, the corresponding redundancy word line or bit line is selected.
The adoption of redundancy in semiconductor memory devices is profitable from the point of view of the increase in the manufacturing process yield only if the increase in the overall chip size is not very high, so that, once the statistical defectiveness of the process is taken into account, the number of "good" memory device chips per wafer is, on average, higher than that obtainable without implementing redundancy. To limit the chip area necessary for implementing redundancy, a careful evaluation of how many redundancy word lines and bit lines are to be provided in the memory matrix is essential, as well as an optimized design of the physical layout of the redundancy circuitry.